1. Field of the Invention
The present invention relates to a method and apparatus for processing of digital images, more particularly to a method and apparatus for scaling a digital image.
2. Description of the Related Art
Digital signal processing of digital images is well known in the art. In digital image processing system, scaling or resizing an image is an important function. A conventional flat display provides various resolutions such as 640 pixels by 480 pixels, 800 pixels by 600 pixels, 1024 pixels by 768 pixels, 1280 pixels by 1024 pixels, while the amount of pixels is adjustable. Different scaling methods cause different clarity and contrast of image output. In traditional duplication and removal method, duplicating a pixel based on required scale produces an addition of pixels with identical intensity. However, by using such method, a saw edge of an image is shown as the image is enlarged by non-integrate times (e.g. 1.33 times) or a much higher enlargement, while a distortion of the image occurs as the image is shrunk. By contrast, another method using linear interpolation by which an addition of pixels is produced depending on location and intensity of adjacent pixels has a better image quality without an obvious saw edge of the scaled image. Such prior art methods are disclosed in U.S. Pat. No. 6,704,463, and references cited from S. Ramachandran, S. Srinivasan, “Design and FPGA Implementation of a Video Scalar with on-chip reduced memory utilization,” dsd, p. 206, Euromicro Symposium on Digital Systems Design (DSD '03), 2003, and A. Ramaswamy, Y. Nijim, “Polyphase Implementation of a Video Scalar”, Signals, Systems and Computers, Asilomar conference, Monterey, Calif., USA, pp. 1691-1694, Vol. 2, 1997, which hereby incorporated by reference. This invention presents a novel scheme to scale the image with filtering method in data unit block (DUB) and removing the opaque area generated during the filtering process.